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R5F10RF8AFP Scheda tecnica(PDF) 43 Page - Renesas Technology Corp |
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R5F10RF8AFP Scheda tecnica(HTML) 43 Page - Renesas Technology Corp |
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43 / 76 page ![]() RL78/L12 2. ELECTRICAL SPECIFICATIONS (TARGET) Page 43 of 73 R01DS0157EJ0001 Rev.0.01 2012.02.20 Under development Preliminary document Specifications in this document are tentative and subject to change. Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin products. UART mode bit width (during communication at different potential) (reference) TxDq RxDq Baud rate error tolerance Baud rate error tolerance Low-bit width High-/Low-bit width High-bit width 1/Transfer rate 1/Transfer rate Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[ Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 1) |
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