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ADS4128 Scheda tecnica(PDF) 21 Page - Texas Instruments

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Il numero della parte ADS4128
Spiegazioni elettronici  12-Bit, 200-MSPS, Ultralow-Power ADC
PDF  61 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS4128 Scheda tecnica(HTML) 21 Page - Texas Instruments

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PowerSupply
AVDD,DRVDD
RESET
SEN
t
1
t
2
t
3
ADS4128
www.ti.com
SBAS578 – MAY 2012
RESET TIMING CHARACTERISTICS
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 11. Reset Timing Diagram
RESET TIMING REQUIREMENTS
Typical values are at +25°C and minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX
= +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay from power-up of AVDD and DRVDD to RESET
t1
Power-on delay
1
ms
pulse active
10
ns
Pulse width of active RESET signal that resets the
t2
Reset pulse width
serial registers
1(1)
µs
t3
Delay from RESET disable to SEN active
100
ns
(1)
The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1 µs, the device can enter
the parallel configuration mode briefly and then return back to serial interface mode.
Copyright © 2012, Texas Instruments Incorporated
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