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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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EBJ41HE4BDFD Scheda tecnica(PDF) 6 Page - Elpida Memory |
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EBJ41HE4BDFD Scheda tecnica(HTML) 6 Page - Elpida Memory |
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6 / 19 page  EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP Data Sheet E1580E30 (Ver. 3.0) 6 Serial PD Matrix -AE -DJ Byte No. Function described Hex Comments Hex Comments 0 Number of serial PD bytes written/SPD device size/CRC coverage 92h 176/256/0-116 92h 176/256/0-116 1 SPD revision 10h Rev.1.0 10h Rev.1.0 2 Key byte/DRAM device type 0Bh DDR3 SDRAM 0Bh DDR3 SDRAM 3 Key byte/module type 01h RDIMM 01h RDIMM 4 SDRAM density and banks 02h 1G bits, 8 banks 02h 1G bits, 8 banks 5 SDRAM addressing 12h 14 rows, 11 columns 12h 14 rows, 11 columns 6 Module nominal voltage, VDD 00h 1.5V 00h 1.5V 7 Module organization 08h 2 ranks/ ×4 bits 08h 2 ranks/ ×4 bits 8 Module memory bus width 0Bh 72 bits/ECC 0Bh 72 bits/ECC 9 Fine timebase (FTB) dividend/divisor 52h 5/2 52h 5/2 10 Medium timebase (MTB) dividend 01h 1 01h 1 11 Medium timebase (MTB) divisor 08h 8 08h 8 12 SDRAM minimum cycle time (tCK (min.)) 0Fh 1.875ns 0Ch 1.5ns 13 Reserved 00h — 00h — 14 SDRAM /CAS latencies supported, LSB 1Ch 6, 7, 8 3Ch 6, 7, 8, 9 15 SDRAM /CAS latencies supported, MSB 00h — 00h — 16 SDRAM minimum /CAS latencies time (tAA (min.)) 69h 13.125ns 69h 13.125ns 17 SDRAM write recovery time (tWR) 78h 15ns 78h 15ns 18 SDRAM minimum /RAS to /CAS delay (tRCD) 69h 13.125ns 69h 13.125ns 19 SDRAM minimum row active to row active delay (tRRD) 3Ch 7.5ns 30h 6.0ns 20 SDRAM minimum row precharge time (tRP) 69h 13.125ns 69h 13.125ns 21 SDRAM upper nibbles for tRAS and tRC 11h — 11h — 22 SDRAM minimum active to precharge time (tRAS), LSB 2Ch 37.5ns 20h 36ns 23 SDRAM minimum active to active /auto-refresh time (tRC), LSB 95h 50.625ns 89h 49.125ns 24 SDRAM minimum refresh recovery time delay (tRFC), LSB 70h 110ns 70h 110ns 25 SDRAM minimum refresh recovery time delay (tRFC), MSB 03h 110ns 03h 110ns 26 SDRAM minimum internal write to read command delay (tWTR) 3Ch 7.5ns 3Ch 7.5ns 27 SDRAM minimum internal read to precharge command delay (tRTP) 3Ch 7.5ns 3Ch 7.5ns 28 Upper nibble for tFAW 01h 37.5ns 00h 30ns 29 Minimum four activate window delay time (tFAW) 2Ch 37.5ns F0h 30ns 30 SDRAM output drivers supported 83h DLL-off, RZQ/6, 7 83h DLL-off, RZQ/6, 7 31 SDRAM refresh options 81h PASR/2X refresh at +85ºC to +95ºC 81h PASR/2X refresh at +85ºC to +95ºC 32 Module thermal sensor 80h Incorporated 80h Incorporated 33 SDRAM device type 00h Standard 00h Standard 34 to 59 Reserved 00h — 00h — |
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