AFE5808ZCF datasheet(59/68 Pages) TI1

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FPGA Clock/

NoisyClock

n×(20~65)MHz

TIJitterCleaner

CDCE72010/

CDCM7005

CDCLVP1208

1-to-8

CLKBuffer

20~65MHz

ADCCLK

8 Synchronized

ADCCLKs

CDCE72010has10

outputsthusthebuffer

maynotbeneededfor

64CHsystems

B0437-01

AFE5808

www.ti.com

SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012

Figure 90. ADC Clock Distribution Network

The AFE5808 ADC clock input can be driven by differential clocks (sine wave, LVPECL or LVDS) or singled

clocks (LVCMOS) similar to CW clocks as shown in Figure 88. In the single-end case, it is recommended that the

use of low jitter square signals (LVCMOS levels, 1.8V amplitude). Please see TI document SLYT075 for further

details on the theory.

The jitter cleaner CDCM7005 or CDCE72010 is suitable to generate the AFE5808’s ADC clock and ensure the

performance for the14bit ADC with 77dBFS SNR. A clock distribution network is shown in Figure 90.

ADC Reference Circuit

The ADC’s voltage reference can be generated internally or provided externally. When the internal reference

mode is selected, the REFP/M becomes output pins and should be floated. When 3[15] =1 and 1[13]=1, the

device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a

1.4V reference voltage and REFP/M must be left open. Since the input impedance of the VREF_IN is high, no

special drive capability is required for the 1.4V voltage reference

The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels.

A typical system would have about 12 octal AFEs on the board. In such a case, it is critical to ensure that the

gain is matched, essentially requiring the reference voltages seen by all the AFEs to be the same. Matching

references within the eight channels of a chip is done by using a single internal reference voltage buffer.

Trimming the reference voltages on each chip during production ensures that the reference voltages are well-

matched across different chips. When the external reference mode is used, a solid reference plane on a printed

circuit board can ensure minimal voltage variation across devices. More information on voltage reference design

can be found in the document SLYT339. The dominant gain variation in the AFE5808 comes from the VCA gain

variation. The gain variation contributed by the ADC reference circuit is much smaller than the VCA gain

variation. Hence, in most systems, using the ADC internal reference mode is sufficient to maintain good gain

matching among multiple AFE5808As. In addition, the internal reference circuit without any external components

achieves satisfactory thermal noise and phase noise performance.

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