REF5050 datasheet(24/43 Pages) TI1

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SYNC

CLK

SYLO

SCSU

CSHD

PULSA

PULSB

Output

SYNC

DAC1282

SBAS490

– DECEMBER 2011

www.ti.com

In sine mode, the SYNC rising edge resets the DAC output to differential 0 V (sine-wave zero-crossing point).

When SYNC is high or low, the output is unaffected. When SYNC is taken from low to high, the output resets on

the following CLK rising edge. SYNC must be pulsed low for a minimum of 2 CLK cycles. The SYNC input can

be applied simultaneous to the DAC and the ADS1282 (ADC in pulse-sync mode).

To synchronize the DAC, observe SYNC to the CLK timing requirements shown in Figure 40. That is, the SYNC

rising edge should be applied before the set-up time or after the hold time specifications. If the SYNC timing

requirement is not met, the DAC may synchronize with one clock cycle timing error.

Figure 40. Sine Mode Synchronization

Table 11. Timing Characteristics for Figure 40(1)

SYMBOL

DESCRIPTION

MIN

UNIT

tSYLO

SYNC pulse width low

tCLK

tSCSU

SYNC rising edge to CLK rising edge setup time

tCSHD

CLK rising edge to SYNC rising edge hold time

(1)

DVDD = 1.65 V to 3.6 V.

In pulse mode, the SYNC pin selects one of two pre-programmed pulse levels. The pulse levels are

programmable from +2.5 V to

–2.5 V in approximately 3-dB steps by pulse level registers PULSA and PULSB.

When SYNC is low, the value of the PULSA register drives the DAC; when SYNC is high, the value of the

PULSB register is the code of the DAC, as shown in Figure 41. When the SYNC pin is changed, the DAC output

updates immediately to the new code.

Figure 41. SYNC Operation in Pulse Mode

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