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CLK

Operational

Status

RSLO

RSTM

Reset

RESET/PWDN

Operational

DAC1282

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SBAS490

– DECEMBER 2011

RESET/PWDN

The RESET/PWDN is a digital input used to power-down and reset the DAC1282. To power-down the DAC, take

the pin low. In power-down mode, the power consumption is reduced to a device leakage level (see the Electrical

Characteristics table). The signal output and digital pin DOUT enters 3-state and the output switch is driven off.

Note that the digital inputs must remain defined as either logic low or logic high; do not float the inputs. Disable

the CLK input to minimize leakage. To exit the power-down state, take the pin high. The DAC1282 is reset after

power-down mode is exited.

The DAC1282 is reset by taking the RESET/PWDN pin low for a minimum of two fCLK cycles and is then taken

back high. The DAC1282 is held in reset for 2 fCLK cycles; after this time, DAC communications may begin, as

shown in Figure 42 and Table 12.

Figure 42. DAC RESET/PWDN

Table 12. Timing Characteristics for Figure 42

SYMBOL

DESCRIPTION

MIN

MAX

UNIT

tRSLO

PWDN/RESET pulse width low for power-down

tCLK

tRSTM

PWDN/RESET high to begin operation

tCLK

AVDD, AVSS, AND DVDD POWER SUPPLIES

The DAC1282 has two power supplies: analog and digital. The analog supply (AVDD, AVSS) is 5 V and can

either be single 5 V or dual (

±2.5 V). The analog supply should be clean and free from noise and ripple. The

DAC1282 regulates the output common-mode voltage to 0.1 V below the mid-point of the analog supply.

Because the analog supply pins draw signal-dependent current and AVSS (pin 14) is internally shared with the

reference input low, trace resistance between AVSS (pin 14) and the AVSS power supply should be minimized or

degraded performance may result. Therefore, connect the external reference ground terminal close to the device

AVSS terminal using a star connection. This configuration helps to minimize power-supply coupling to the

reference input.

DVDD is the digital supply used to power both the internal digital and the device I/O pins. The allowable range of

DVDD is 1.65 V to 3.6 V.

The power supplies can be sequenced on or off in any order, but the analog or digital inputs should never

exceed AVDD or AVSS, or DVDD, respectively. In such an event, the internal ESD protection diodes may begin

to conduct. The input current must always be limited as specified in the Absolute Maximum Ratings table.

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