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CXD3003 Scheda tecnica(PDF) 12 Page - Sony Corporation |
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CXD3003 Scheda tecnica(HTML) 12 Page - Sony Corporation |
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12 / 137 page ![]() – 12 – CXD3003R (4) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 3.3V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C) COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency fCOUT fMIRR fDFCTH 40 40 5 kHz kHz kHz ∗1 ∗2 ∗3 Item Symbol Min. Typ. Max. Unit Conditions ∗1 When using a high-speed traverse TZC. ∗2 When the RF signal continuously satisfies the following conditions during the above traverse. • A = 0.11VDD to 0.23VDD • ≤ 25% ∗3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. (3) SCLK pin SCLK frequency SCLK pulse width Delay time fSCLK tSPW tDLS 31.3 15 16 MHz ns µs Item Symbol Min. Typ. Max. Unit tSPW tDLS 1/fSCLK MSB LSB ••• ••• XLAT SCLK Serial Read Out Data (SENS) A B B A + B |
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