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CXD3003 Scheda tecnica(PDF) 41 Page - Sony Corporation |
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CXD3003 Scheda tecnica(HTML) 41 Page - Sony Corporation |
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41 / 137 page ![]() – 41 – CXD3003R Command Data 1 Function specification DCLV ON-OFF DSPB ON-OFF A.SEQ ON-OFF D.PLL ON-OFF D23 D22 D21 D20 Data 2 BiliGL MAIN BiliGL SUB FLFC D19 D18 D17 XWOC D16 $9X commands Command bit DCLV on/off = 0 In CLVS mode FSW = low, MON = high, MDS = Z; MDP = servo control signal, carrier frequency of 230Hz at TB = 0 and 460Hz at TB = 1. FSW = Z, MON = high; MDS = speed control signal, carrier frequency of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz. When DCLV PWM and MD = 1 (Prohibited in CLV-W and CAV-W modes) MDS = PWM polarity signal, carrier frequency of 132kHz MDP = PWM absolute value output (binary), carrier frequency of 132kHz When DCLV PWM and MD = 0 MDS = Z MDP = ternary PWM output, carrier frequency of 132kHz In CLVP mode In CLVS and CLVP modes DCLV on/off = 1 (FSW, MON not required) CLV mode Contents When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1. Command bit DSPB = 0 DSPB = 1 Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) Processing FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed. Command bit DPLL = 0 ∗ DPLL = 1 RFPLL is analog. PDO, VCOI and VCOO are used. RFPLL is digital. PDO is high impedance. Meaning Command bit BiliGL SUB = 0 BiliGL SUB = 1 STEREO SUB MAIN Mute BiliGL MAIN = 0 BiliGL MAIN = 1 Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. ∗ External parts for the FILI, FILO and PCO pins are required even when analog PLL is selected. |
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