CXD3017Q datasheet(49/117 Pages) SONY

Il numero della parte	CXD3017Q

Spiegazioni elettronici	CD Digital Signal Processor with Built-in Digital Servo and DAC

PDF	117 Pages

Scroll/Zoom	100%

Produttore elettronici	SONY [Sony Corporation]

Homepage	http://www.sony.co.jp

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CXD3017Q

§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to

11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,

T, that is the channel clock, is necessary.

In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the

spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 3-1.

The CXD3017Q has a built-in three-stage PLL.

• The first-stage PLL regenerates the high-frequency clock needed by the second-stage digital PLL.

• The second-stage PLL is a digital PLL that regenerates the actual channel clock.

Block Diagram 3-1

X'tal

XTSL

OSC

1/M

1/N

VCO1

VCOSEL1

1/K

(KSL3, 2)

Digital PLL

RFPLL

PCO

FILI

FILO

CLTV

CXD3017Q

CXD3017Q Scheda tecnica(PDF) 49 Page - Sony Corporation