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L6360 Scheda tecnica(PDF) 43 Page - STMicroelectronics |
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L6360 Scheda tecnica(HTML) 43 Page - STMicroelectronics |
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43 / 65 page ![]() L6360 Device configuration Doc ID 022817 Rev 2 43/65 1st frame Bit 7÷1: L6360 address Bit 0: Direction 2nd frame Bit 7÷0: Data register 3rd frame Bit 7÷5: Parity bits Bit 4: Unused Bit 3÷0: Register address The parity check bits are calculated as shown in Equation 2: Equation 2 P0 = D7 ⊕ D6 ⊕ D5 ⊕ D4 ⊕ D3 ⊕ D2 ⊕ D1 ⊕ D0 P1 = D7 ⊕ D5 ⊕ D3 ⊕ D1 (odd parity) P2 = D6 ⊕ D4 ⊕ D2 ⊕ D0 (even parity) If parity error occurs, the register are not overwritten. Table 27. Current Write mode direction bit W bit Master Slave 0 Write mode Read mode 1 Read mode Write mode |
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