WM8912 datasheet(87/128 Pages) WOLFSON

87 / 128 page

Production Data

WM8912

PD, Rev 4.0, September 2010

Index addresses 0 to 24 may be programmed to users’ own settings at any time, as described in

“Programming a Sequence”. Users’ own settings remain in memory and are not affected by software

resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is

powered down.

START-UP SEQUENCE

The Start-up sequence is initiated by writing 0100h to Register R111 (6Fh). This single operation

starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence defined in

Table 59.

For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately

300ms to run.

Note that, for fast startup, step 18 may be overwritten with dummy data in order to achieve startup

within 50ms (see “Quick Start-Up and Shutdown”).

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

0 (00h)

R4 (04h)

5 bits

Bit 0

1Ah

BIAS_ENA = 0

(delay = 0.5625ms)

1 (01h)

R5 (05h)

8 bits

Bit 0

47h

VMID_RES [1:0] = 11b

VMID_ENA = 1

(delay = 4.5ms)

2 (02h)

R5 (05h)

2 bits

Bit 1

01h

VMID_RES [1:0] = 01b

(delay = 0.5625ms)

3 (03h)

R4 (04h)

1 bit

Bit 0

01h

BIAS_ENA = 1

(delay = 0.5625ms)

4 (04h)

R14 (0Eh)

2 bits

Bit 0

03h

HPL_PGA_ENA = 1

HPR_PGA_ENA = 1

(delay = 0.5625ms)

5 (05h)

R15 (0Fh)

2 bits

Bit 0

03h

LINEOUTL_PGA_ENA = 1

LINEOUTR_PGA_ENA = 1

(delay = 0.5625ms)

6 (06h)

R22 (16h)

1 bit

Bit 1

01h

CLK_DSP_ENA = 1

(delay = 0.5625ms)

7 (07h)

R18 (12h)

2 bits

Bit 2

03h

DACL_ENA = 1

DACR_ENA = 1

(delay = 2.5ms)

8 (08h)

R255 (FFh)

1 bit

Bit 0

00h

Dummy Write for expansion

(delay = 0.5625ms)

9 (09h)

R4 (04h)

1 bit

Bit 4

00h

(delay = 0.5625ms)

10 (0Ah)

R98 (62h)

1 bit

Bit 0

01h

CP_ENA = 1

(delay = 4.5ms)

11 (0Bh)

R255 (FFh)

1 bit

Bit 0

00h

Dummy Write for expansion

(delay = 0.5625ms)

12 (0Ch)

R90 (5Ah)

8 bits

Bit 0

11h

HPL_ENA = 1

HPR_ENA = 1

(delay = 0.5625ms)

13 (0Dh)

R94 (5Eh)

8 bits

Bit 0

11h

LINEOUTL_ENA = 1

LINEOUTR_ENA = 1

(delay = 0.5625ms)

14 (0Eh)

R90 (5Ah)

8 bits

Bit 0

33h

HPL_ENA_DLY = 1

HPR_ENA_DLY = 1

(delay = 0.5625ms)

15 (0Fh)

R94 (5Eh)

8 bits

Bit 0

33h

LINEOUTL_ENA_DLY = 1

LINEOUTR_ENA_DLY = 1

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