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PXR40 Scheda tecnica(PDF) 72 Page - Freescale Semiconductor, Inc |
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PXR40 Scheda tecnica(HTML) 72 Page - Freescale Semiconductor, Inc |
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72 / 100 page ![]() PXR40 Microcontroller Data Sheet, Rev. 1 Electrical characteristics Freescale Semiconductor 72 Table 24. PFCPR1 settings vs. frequency of operation1 1 Illegal combinations exist. Use entries from the same row in this table. Spec Clock Mode Maximum Frequency2 (MHz) 2 This is the nominal maximum frequency of operation: platform runs at f sys/2 in Enhanced Mode . APC = RWSC WWSC DPFEN3 3 For maximum flash performance, set to 0b1. IPFEN3 PFLIM4 4 For maximum flash performance, set to 0b10. BFEN5 5 For maximum flash performance, set to 0b1. Core fsys Platform fplatf 1 Enhanced 264 MHz6 6 This is the nominal maximum frequency of operation in Enhanced Mode. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(fsys)+2% FM and 132 Mhz platform clock (fplatf)+ 2% FM. 132 MHz6 0b011 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 2 Enhanced/ Full 200 MHz 100 MHz 0b010 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 3 Legacy 132 MHz 132 MHz 0b100 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 Default setting after reset: 0b111 0b11 0b00 0b00 0b00 0b0 |
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