PXR40 datasheet(73/100 Pages) FREESCALE

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Electrical characteristics

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

5.11

AC specifications

5.11.1

Clocking

Figure 8 shows the operating frequency domains of various blocks on PXR40.

Figure 8. PXR40 block operating frequency domain diagram

Table 25 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see

Table 26 and Table 27 for descriptions of bit settings).

Table 25. PXR40 operating frequencies1, 2

1 The values in the table are specified at:

VDD = 1.02 V to 1.32 V

VDDE = 3.0 V to 3.6 V

VDDEH = 4.5 V to 5.5 V

VDD33 and VDDSYN = 3.0 V to 3.6 V

TA =TL to TH.

Mode

SIU_ECCR

[EBDF[0:1]]3

fsys

(core)

fplatf

(platform and all blocks

except eTPU)

fetpu

(eTPU, eTPU RAM,

and NDEDI)

febi_cal

4,5

Unit

Enhanced

264

132

MHz

Full

200

100

200

MHz

Legacy

132

MHz

PLL

CORE

PLATFORM /

eTPU /

EBI

CAL BUS

EXTAL

D_CLKOUT

fplatf

Note: tcycsys = 1 / fsys

tcyc =1 / fplatf

2 = divide-by-2

 X = divide-by-X, depending on SIU_SYSDIV[BYPASS]

and SIU_SYSDIV[SYSCLKDIV].

BLOCKS /

(D_CLKOUT is not available

on all packages and cannot

be programmed for faster

than fsys/2.)

 2

PLLCFG[0:1]

SIU_SYSDIV[SYSCLKDIV[0:1]]

IPG DIV SEL

ETPU DIV SEL

SIU_SYSDIV[IPCLKDIV[0:1]]

fetpu

SYSDIV

 X

FLASH

NDEDI

DIV

febi_cal

SIU_SYSDIV[BYPASS]

X = 2, 4, 8, or 16

X=1

fsys

SIU_ECCR[EBDF[0:1]]

fperiph

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