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CY8C58LP Scheda tecnica(PDF) 39 Page - Cypress Semiconductor

Il numero della parte CY8C58LP
Spiegazioni elettronici  Programmable System-on-Chip (PSoC짰)
PDF  122 Pages
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C58LP Scheda tecnica(HTML) 39 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5LP: CY8C58LP Family
Datasheet
Document Number: 001-84932 Rev. **
Page 39 of 122
Figure 7-4. Datapath Top Level
7.2.2.1
Working Registers
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
7.2.2.2
Dynamic Datapath Configuration RAM
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
x 16-bit configuration RAM, which stores eight unique 16-bit wide
configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
ALU
The ALU performs eight general purpose functions. They are:
■ Increment
■ Decrement
■ Add
■ Subtract
■ Logical AND
■ Logical OR
■ Logical XOR
■ Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register
Independent of the ALU operation, these functions are available:
■ Shift left
■ Shift right
■ Nibble swap
■ Bitwise OR mask
A0
A1
D0
D1
PI
ALU
Mask
Shift
Data Registers
Output
Muxes
F1
F0
FIFOs
Accumulators
PO
A0
A1
D0
D1
Output to
Programmable
Routing
Chaining
Parallel Input/Output
(To/From Programmable Routing)
Input from
Programmable
Routing
Input
Muxes
To/From
Next
Datapath
To/From
Previous
Datapath
PHUB System Bus
R/W Access to All
Registers
6
6
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumu-
lators or ALU. Each FIFO is four
bytes deep.



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