CY8C58LP datasheet(19/122 Pages) CYPRESS

19 / 122 page

PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 19 of 122

5.6 External Memory Interface

CY8C58LP provides an external memory interface (EMIF) for

connecting to external memory devices. The connection allows

read and write accesses to external memories. The EMIF

operates in conjunction with UDBs, I/O ports, and other

hardware to generate external memory address and control

signals. At 33 MHz, each memory access cycle takes four bus

clock cycles.

Figure 5-1 is the EMIF block diagram. The EMIF supports

synchronous and asynchronous memories. The CY8C58LP only

supports one type of external memory device at a time.

External memory is located in the Cortex-M3 external RAM

space; it can use up to 24 address bits. See Memory Map on

page 20. The memory can be 8 or 16 bits wide. Cortex-M3

instructions can be fetched/executed from external memory,

although at a slower rate than from flash. There is no provision

for code security in external memory. If code must be kept

secure, then it should be placed in internal flash. See Flash

Security on page 17 and Device Security on page 60.

Figure 5-1. EMIF Block Diagram

PHUB

IO IF

UDB

EMIF

I/O

PORTs

I/O

PORTs

I/O

PORTs

Data,

Address,

and Control

Signals

Data,

Address,

and Control

Signals

Address Signals

Data Signals

Control Signals

Data,

Address,

and Control

Signals

EM Control

Signals

Other

Control

Signals

DSI Dynamic Output

Control

DSI to Port

Control

External_ MEM_ DATA[15:0]

External_ MEM_ ADDR[23:0]

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