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OPTION_REG Scheda tecnica(PDF) 214 Page - Microchip Technology

Il numero della parte OPTION_REG
Spiegazioni elettronici  Digitally Enhanced Power Analog Controller with Integrated Synchronous Driver
PDF  222 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

OPTION_REG Scheda tecnica(HTML) 214 Page - Microchip Technology

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MCP19111
DS22331A-page 214
 2013 Microchip Technology Inc.
R
Reader Response ............................................................. 218
Read-Modify-Write Operations.......................................... 191
Register
OVFCON (Output Voltage Set Point Fine Control) ..... 45
Registers
ABECON (Analog Block Enable Control).................... 50
ADCON0 (ADC Control 0) ........................................ 127
ADCON1 (ADC Control 1) ........................................ 128
ADRESH (ADC Result High) with ADFM = 0)........... 128
ADRESL (ADC Result Low) with ADFM = 0) ............ 128
ANSELA (Analog Select GPA).................................. 113
ANSELB (Analog Select GPB).................................. 116
APFCON (Alternate Pin Function Control)................ 110
ATSTCON (Analog Bench Test Control) .................... 55
BUFFCON (Unity Gain Buffer Control) ....................... 56
CALWD1 (Calibration Word 1) .................................... 57
CALWD2 (Calibration Word 2) .................................... 58
CALWD3 (Calibration Word 3) .................................... 59
CALWD4 (Calibration Word 4) .................................... 60
CALWD5 (Calibration Word 5) .................................... 61
CALWD6 (Calibration Word 6) .................................... 62
CALWD7 (Calibration Word 7) .................................... 63
CMPZCON (Compensation Setting Control) .............. 41
CSDGCON (Voltage For Zero Current Control).......... 39
CSGSCON (Current Sense AC Gain Control) ............ 38
DEADCON (Driver Dead Time Control) ...................... 44
DEVICEID (Device ID) ................................................ 80
INTCON (Interrupt Control) ......................................... 93
IOCA (Interrupt-on-Change PORTGPA) ................... 120
IOCB (Interrupt-on-Change PORTGPB) ................... 120
LPCRCON (Slope Compensation Ramp Control)....... 42
OCCON (Output OverCurrent Control) ....................... 37
OOVCON (Output OverVoltage Detect Level Control)46
OPTION_REG (Option) .............................................. 75
OSCTUNE (Oscillator Tuning) .................................... 81
OUVCON (Output Under Voltage Detect Level Control)
46
OVCCON (Output Voltage Set Point Coarse Control) 45
PCON (Power Control) ........................................ 85, 90
PE1(Analog Peripheral Enable 1 Control) .................. 48
PIE1 (Peripheral Interrupt Enable) .............................. 94
PIR1 (Peripheral Interrupt Flag) .................................. 96
PIR2 (Peripheral Interrupt Flag) .................................. 97
PMADRL (Program Memory Address)...................... 104
PMCON1 (Program Memory Control) ....................... 105
PMDATH (Program Memory Data) ........................... 104
PMDATL (Program Memory Data)............................ 104
PMDRH (Program Memory Address)........................ 105
PORTGPA ................................................................ 111
PORTGPB ................................................................ 115
RELEFF (Relative Efficiency Measurement) .............. 65
Reset Values............................................................... 87
SLVGNCON (MASTER Error Signal Input Gain Control)
43
Special Registers Summary...................... 71, 72, 73, 74
SSPCON1(SSP Control)........................................... 183
SSPSTAT (SSP Status) ............................................ 182
SSPxADD (MSSPx Address and Baud Rate, I2C Mode)
186, 187
SSPxCON1 (MSSPx Control 1) ................................ 183
SSPxCON2 (SSPx Control 2) ................................... 184
SSPxCON3 (SSPx Control 3) ................................... 185
SSPxMSK (SSPx Mask) ................................... 186, 187
SSPxSTAT (SSPx Status) ........................................ 182
STATUS ..................................................................... 69
T1CON (Timer1 Control) .......................................... 136
TRISA (Tri-State PORTA)......................................... 112
TRISGPB ( PORTGPB Tri-State) ............................. 115
TXCON ..................................................................... 139
VINLVL (Input Under Voltage Lockout Control).......... 35
VZCCON (Voltage for Zero Current Control).............. 40
WPUB (Weak Pull-up PORTB)................................. 112
WPUGPA
Weak Pull-up PORTGPA.................................. 112
WPUGPB (Weak Pull-up PORTGPB) ...................... 116
Relative Efficiency Circuity Control ..................................... 49
Relative Efficiency Measurement ....................................... 65
Procedure ................................................................... 65
Relative Efficiency Measurement Control........................... 49
Reset .................................................................................. 83
Determining Causes ................................................... 89
Resets................................................................................. 83
Associated Registers .................................................. 90
Revision History................................................................ 209
S
Signal Chain Control ........................................................... 49
Sleep
Wake-up from ............................................................. 99
Wake-up Using Interrupts ......................................... 100
Slope Compensation .................................................... 16, 42
Slope Compensation Control.............................................. 49
Software Simulator (MPLAB SIM) .................................... 203
Special Event Trigger ....................................................... 126
Special Function Registers ................................................. 69
Special Registers Summary
Bank 0 ........................................................................ 71
Bank 1 ........................................................................ 72
Bank 2 ........................................................................ 73
Bank 3 ........................................................................ 74
SSPxADD Register................................................... 186, 187
SSPxCON1 Register ........................................................ 183
SSPxCON2 Register ........................................................ 184
SSPxCON3 Register ........................................................ 185
SSPxMSK Register................................................... 186, 187
SSPxOV............................................................................ 172
SSPxOV Status Flag ........................................................ 172
SSPxSTAT Register ......................................................... 182
R/W Bit ..................................................................... 151
Stack................................................................................... 76
Start-up Sequence .............................................................. 85
STATUS Register ............................................................... 69
Switching Frequency .......................................................... 16
System Bench Testing .................................................. 20, 55



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