REV. A

ADP3610

–6–

THEORY OF OPERATION

The ADP3610 is an unregulated switched capacitor voltage

doubler that provides an output voltage greater than 5.4 V from

a +3.0 V to +3.6 V input. The unique push-pull voltage dou-

bling architecture allows it to deliver a maximum of 320 mA

output current. A typical application circuit, as shown in Figure

20, requires five small external capacitors. The ADP3610 has an

internal 1 MHz oscillator that is divided by two and used to

generate two nonoverlapping phase clocks.

The basic principle behind a conventional switched capacitor

voltage doubler is shown in Figure 15. During phase one, S1

and S2 are ON, charging the pump capacitor to the input volt-

age. In phase two, switches S1 and S2 are turned OFF and S3

and S4 are turned ON. During phase two, the pump capacitor

is placed in series with the input voltage, thereby charging the

output capacitor to the sum of input voltage and pump ca-

pacitor voltage, resulting in voltage doubling at the output

terminal.

+

S2

S1

S3

S4

C

P

A

PHASE

1

PHASE

2

B

B

A

A

B

Figure 15. Conventional Voltage Doubler Configuration

The ADP3610 has two sets of switched capacitor voltage dou-

blers connected in parallel delivering charge to the output as

shown in Figure 16.

+

S8

B

A

CP2

S6

S7

S2

S3

A

A

B

CP1

+

S5

S4

S1

B

B

A

Figure 16. Switch Configuration Charging the Pump

Capacitor

The two voltage doublers run in opposite phases, i.e., when one

pump capacitor is being charged, the other is charging the out-

put, as shown in Figure 17. In this architecture, one of the

pump capacitors is always delivering charge to the output. As a

result, output ripple is at a frequency that is double the switch-

ing frequency. This allows the use of a smaller output capacitor

compared to a conventional voltage doubler.

PHASE 1

(a)

S8

CP2

S7

S2

CP1

A

A

A

+

+

S3

B

S4

B

S5

B

S6

B

S1

A

PHASE 2

(b)

B

S6

S3

S5

S4

B

+

+

CP1

CP2

B

B

S8

A

S1

A

A

S2

A

S7

Figure 17. (a) Phase 1 “Push” Charging

(b) Phase 2 “Pull” Charging

Overvoltage Protection

The input voltage is scaled with a resistor network and com-

pared to the bandgap reference voltage of 1.25 V by a 50 mV

hysteresis comparator. When the input voltage exceeds 4.0 V,

the overvoltage protection signal stops the oscillator.

R1

R2

ADP3610

BANDGAP

= 1.25V

OSC

EN

50mV

Figure 18. Overvoltage Protection

Shutdown Mode

The ADP3610’s output can be disabled by pulling the SD pin

high to a TTL/CMOS logic compatible level which will stop the

internal oscillator. In shutdown mode, all analog circuitry in-

cluding overvoltage protection is shut off, thereby reducing the

quiescent current to 10

µA typical. Applying a digital low level

or tying the SD pin to ground will turn on the output. If the

shutdown feature is not used, SD pin should be tied to the

ground pin. The output voltage in shutdown mode is approxi-