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ADP3610 Scheda tecnica(PDF) 7 Page - Analog Devices |
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ADP3610 Scheda tecnica(HTML) 7 Page - Analog Devices |
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7 / 10 page ![]() REV. A ADP3610 –7– APPLICATION INFORMATION Capacitor Selection The ADP3610’s high internal oscillator frequency permits the use of small capacitors for both the pump and the output ca- pacitors. For a given load current, factors affecting the output voltage performance are: • Pump (CP) and output (CO) capacitance • ESR of the CP and CO When selecting the capacitors, keep in mind that not all manu- facturers guarantee capacitor ESR in the range required by the circuit. In general, the capacitor’s ESR is inversely proportional to its physical size, so larger capacitance values and higher volt- age ratings tend to reduce ESR. Since the ESR is also a function of the operating frequency, when selecting a capacitor, make sure its value is rated at the circuit’s operating frequency. An- other factor affecting capacitor performance is temperature. Fig- ure 19 illustrates the temperature effect on various capacitors. Aluminium electrolytic capacitors lose their capacitance at low temperatures and their ESR increases considerably. Some capacitor technologies do offer improved performance over temperature; for example, certain tantalum capacitors provide good low temperature ESR but at a higher cost. Table II pro- vides the ratings for different types of capacitor technologies to help the designer select the right capacitors for the application. The exact values of CIN and CO are not critical. However, low ESR capacitors such as solid tantalum and multilayer ceramic capacitors are recommended to minimize voltage loss at high currents. Table III shows a partial list of the recommended low ESR capacitor manufacturers. Input Capacitor A small 1 µF input bypass capacitor, preferably with low ESR, such as tantalum or multilayer ceramic, is recommended to reduce noise and supply transients and supply part of the peak input current drawn by the ADP3610. A large capacitor is rec- ommended if the input supply is connected to the ADP3610 through long leads, or if the pulse current drawn by the device might affect other circuitry through supply coupling. Output Capacitor The output capacitor (CO) is alternately charged to the sum of input voltage and pump capacitor voltage when CP is switched in series with CO. The ESR of CO introduces steps in the VOUT waveform whenever the charge pump charges CO, which tends to increase VOUT ripple. Thus, ceramic or tantalum capacitors are recommended for CO to minimize ripple on the output. Note that as the capacitor value increases beyond the point where the dominant contribution to the output ripple is due to the ESR, no significant reduction in VOUT ripple is achieved by added capacitance. Multiple smaller capacitors can be connected in parallel to yield lower ESR and potential cost savings. For lighter loads, propor- tionally smaller capacitors are required. To reduce high fre- quency noise, bypass the output with a 0.1 µF ceramic capacitor. Pump Capacitor The ADP3610 alternately charges CP to the input voltage when it is switched in parallel with the input supply, and then trans- fers charge to CO when it is switched in series with the input and connected to the output. ALUMINUM CERAMIC TANTALUM ORGANIC SEMIC TEMPERATURE – C 10 1.0 0.01 –50 0 100 50 0.1 TANTALUM ORGANIC SEMIC CERAMIC ALUMINUM Figure 19. ESR vs. Temperature Power Dissipation The power dissipation of the ADP3610 circuit must be limited so the junction temperature of the device does not exceed the maximum junction temperature rating. Total power dissipation is calculated as follows: PD = (2 VIN – VOUT) IOUT + VIN (IS) Where IOUT and IS are output current and supply current, VIN and VOUT are input and output voltages respectively. For example: assuming worst case conditions, VIN = 3 V, VOUT = 5.62 V, IOUT = 320 mA and IS = 14 mA. Calculated device power dissipation is: PD ≈ (6 V – 5.62 V) × 0.32 + 3 × (0.014) = 163.6 mW The proprietary thermal coastline package used in the ADP3610 has a thermal resistance of 102 °C/W. Therefore, the rise in junction temperature for this application would be: TRISE = 0.164 W × 102°C/W = 16.7°C General Board Layout Guidelines Since the ADP3610’s internal switches turn on and off very fast, good PC board layout practices are critical to ensure optimal operation of the device. Improper layouts will result in poor load regulation, especially under heavy loads. Following these simple layout guidelines will improve output performance. 1. Use adequate ground and power traces or planes. 2. Use single point ground for device ground and input and output capacitor grounds. 3. Keep external components as close to the device as possible. 4. Use short traces from the input and output capacitors to the input and output pins respectively. 5. All multiple GND, VIN and VOUT pins must be connected together for proper operation. |
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