OR3LP26B datasheet(121/184 Pages) AGERE

Il numero della parte	OR3LP26B

Spiegazioni elettronici	Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

PDF	184 Pages

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Produttore elettronici	AGERE [Agere Systems]

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Lucent Technologies Inc.

121

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Target Read Memory Burst, No Delayed Transaction

Figure 47 (PCI bus) and Figure 46 (FPGA bus) show the timing for a Target memory burst read of four Quadwords

handled as a nondelayed transaction. Figure 47 shows the timing on the PCI interface is similar to that of an I/O

read (Figure 40) except that stop is not asserted here to cause disconnect with data, but rather the operation is free

to continue since it is allowed to complete on the source (PCI) bus before it completes on the destination (FPGA)

bus.

5-8861(F).a

Figure 47. Target Read Memory Burst, No Delayed (PCI Bus, 32-Bit)

Tn0

Tn1

Tn2

Tn3

Tn4

Tn5

Tn6

ADRS

CMD

BE0

BE1

BE2

BE3

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

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