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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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OR3LP26B Scheda tecnica(PDF) 63 Page - Agere Systems |
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OR3LP26B Scheda tecnica(HTML) 63 Page - Agere Systems |
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63 / 184 page  Lucent Technologies Inc. 63 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. PCI Bus Core Detailed Description Dual Port (continued) Target Read I/O, No Delayed Transaction Figure 18 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target I/O read that is handled as an immedi- ate execution; that is, the operation completes on the PCI bus immediately and then is presented to the FPGA via the FPGA interface. The FPGA application indicates its desire to do this by deasserting signal deltrn. The PCI core Target terminates the I/O read request by disconnecting with data on the first data word, thus disallowing bursting. The PCI interface timing shown in Figure 18 is identical to the timing of the third (final) transaction of Target I/O read, delayed transaction (Figure 17), which shows a Target I/O read with delayed transaction. Also, the FPGA interface timing is as shown in Figure 20, regardless of whether delayed transactions are enabled. 5-8857(F).a Figure 18. Target I/O Read, Not Delayed (PCI Bus, 64-Bit) T0 T1 T2 T3 Tn0 Tn1 Tn2 Tn3 X ADDRESS X X DATA X X CMD BYTE ENABLES BYTE ENABLES X clk framen ad c_ben irdyn devseln trdyn stopn |
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