OR3LP26B datasheet(141/184 Pages) AGERE

141 / 184 page

Lucent Technologies Inc.

141

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 56. OR3LP26B Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

The pin-to-pin timing parameters in this table should be used instead of results reported by

ORCA Foundry.

The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay

includes both the input buffer delay and the clock routing to the PIO clock input.

5-4847(F).b

Figure 54. Input to ExpressCLK Setup/Hold Time

Description

(TJ = 85 °C, VDD = min)

Min

Max

Unit

Input to ECLK Setup Time (middle ECLK pin)

0.97

—

Input to ECLK Setup Time (middle ECLK pin, delayed data input)

9.98

—

Input to ECLK Setup Time (corner ECLK pin)

0.0

—

Input to ECLK Setup Time (corner ECLK pin, delayed data input)

8.11

—

Input to ECLK Hold Time (middle ECLK pin)

0.0

—

Input to ECLK Hold Time (middle ECLK pin, delayed data input)

0.0

—

Input to ECLK Hold Time (corner ECLK pin)

0.0

—

Input to ECLK Hold Time (corner ECLK pin, delayed data input)

0.0

—

CLK

INPUT

PIO ECLK LATCH

CLKCNTRL

ECLK

OR3LP26B Scheda tecnica(PDF) 141 Page - Agere Systems

OR3LP26B Scheda tecnica(HTML) 141 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL