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Timing Information

Configuration Devices for SRAM-Based LUT Devices

January 2012

Altera Corporation

Timing Information

Figure 5 shows the timing waveform when using a configuration device.

Table 8 lists the timing parameters when using EPC2 devices at 3.3 V.

Figure 5. Timing Waveform Using a Configuration Device

Note to Figure 5:

(1) The EPC2 device drives DCLK low and DATA high after configuration. The EPC1 and EPC1441 devices drive DCLK low and tri-state DATA after

configuration.

DD

D

D

0

1

2

3

Tri-State

User Mode

(1)

Tri-State

OE/nSTATUS

nCS/CONF_DONE

DCLK

DATA

User I/O

INIT_DONE

nINIT_CONF or VCC/nCONFIG

Table 8. Timing Parameters when Using EPC2 devices at 3.3 V

Symbol

Parameter

Min

Typ

Max

Units

POR delay (1)

——

200

ms

OE

high to DATA output enabled

—

—

80

ns

OE

high to first rising edge on DCLK

——

300

ns

Data

setup time before rising edge on DCLK

30

—

—

ns

Data

hold time after rising edge on DCLK

0—

—

ns

DCLK

to DATA out

—

—

30

ns

DCLK

to DATA enable/disable

—

—

30

ns

DCLK

frequency

5

7.7

12.5

MHz

DCLK

high time for the first device in the configuration chain

40

65

100

ns

DCLK

low time for the first device in the configuration chain

40

65

100

ns

DCLK

high time for subsequent devices

40

—

—

ns

DCLK

low time for subsequent devices

40

—

—

ns

DCLK

rising edge to nCASC

—

—

25

ns

nCS

to nCASC cascade delay

—

—

15

ns

OE

low pulse width (reset) to guarantee counter reset

100

—

—

ns

OE

low (reset) to DCLK disable delay

—

—

30

ns

OE

low (reset) to nCASC delay

—

—

30

ns

Note to Table 8:

(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.