MPC8314VRADDA datasheet(100/101 Pages) FREESCALE

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MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

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Freescale Semiconductor

Revision History

27 Revision History

This table summarizes a revision history for this document.

Table 79. Revision History

Revision

Date

Substantive Change(s)

11/2011

• In Table 66:

–

Corrected Note 10 to pull down.

–

Added pull up information.

11/2011

• Added Notes 4, 5, 6, and 7 in Table 2.

•In Table 6:

–

Decoupled PCI_CLK and SYS_CLK_IN rise and fall times.

–

Relaxed maximum rise/fall time of SYS_CLK_IN from 1.2 ns to 4 ns.

–

Modified Note 2.

–

Updated SYS_CLK_IN/PCI_CLK frequency from 66 MHz to 66.67 MHz.

• Added Note 4 to Table 9.

• Added a note stating “eTSEC should be interfaced with peripheral operating at same voltage level.”

in Section 9.1.1, “MII, RMII, RGMII, and RTBI DC Electrical Characteristics.”

• Added a note in Table 26 stating “The frequency of RX_CLK should not exceed the TX_CLK by

more than 300 ppm."

• Added a note in Table 29 stating “The frequency of RX_CLK should not exceed the GTX_CLK125

by more than 300 ppm

•In Table 42, changed min/max values of tCLK_TOL from 0.05 to 0.005.

• Added tLALEHOV parameter to Table 44

• Replaced 50 with 50

in Section 16.5, “Receiver Compliance Eye Diagrams.”

•In Table 66:

–

Added Pull up and Pull down information.

–

Removed Note 2 from TSEC_MDIO.

• Removed configuration 2 from Table 73.

• Removed Preliminary from Section 24, “Thermal.”

• Removed MDIO signal from Section 25.7, “Pull-Up Resistor Requirements” as this signal is not

open drain.

• Replaced LCCR with LCRR throughout.

• Replaced SYS_CLKIN with SYS_CLK_IN throughout.

• Replaced all LBIUCM with LBCM.

• Replaced all SYS_CR_CLK_IN and SYS_CR_CLK_OUT with SYS_XTAL_IN and

SYS_XTAL_OUT, respectively. Replaced all USB_CR_CLK_IN and USB_CR_CLK_OUT with

USB_XTAL_IN and USB_XTAL_OUT, respectively.

• Added rise/fall time spec for TDM CLK

05/2009

Initial public release

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