CDPCLK7 datasheet(241/274 Pages) ALTERA

241 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–83

Remote System Upgrade

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

■

Cyclone III device family logic array triggered a reconfiguration cycle, possibly

after downloading a new application configuration image

■

External configuration reset (nCONFIG) assertion

■

User watchdog timer time out

Table 9–28 lists the contents of the current state logic in the status register, when the

remote system upgrade master state machine is in factory configuration or

application configuration accessing the factory information or application

information respectively, and the MSEL pin setting is set to AS or AP configuration

scheme. The status register bit in Table 9–28 lists the bit positions in a 32-bit logic.

The previous two application configurations are available in the previous state

registers (previous state register 1 and previous state register 2), but only for

debugging purposes.

Table 9–28. Remote System Upgrade Current State Logic Contents In Status Register (1)

Current State Logic

Status Register Bit

Definition

Description

Factory information (2)

31:30

Master State Machine

current state

The current state of the RSU master

state machine

29:24

Reserved bits

Padding bits that are set to all 0's

23:0

Boot address

The current 24-bit boot address that was

used by the configuration scheme as the

start address to load the current

configuration.

Application information

part 1 (3)

31:30

Master State Machine

current state

The current state of the RSU master

state machine

User watchdog timer

enable bit

The current state of the user watchdog

enable, which is active high

28:0

User watchdog timer

time-out value

The current entire 29-bit

watchdog time-out value

Application information

part 2 (3)

31:30

Master State Machine

current state

The current state of the RSU master

state machine

29:24

Reserved bits

Padding bits that are set to all 0’s

23:0

Boot address

The current 24-bit boot address that was

used by the configuration scheme as the

start address to load the current

configuration

Notes to Table 9–28:

(1) The MSEL pin setting is in the AS or AP configuration scheme.

(2) The RSU master state machine is in factory configuration.

(3) The RSU master state machine is in application configuration.

CDPCLK7 Scheda tecnica(PDF) 241 Page - Altera Corporation

CDPCLK7 Scheda tecnica(HTML) 241 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL