TP8044AH-R0117 datasheet(33/65 Pages) INNOVASIC

33 / 65 page

IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

Customer Support:

Page 33 of 65

1-888-824-4184

Bit [2]—OV → (PSW.7) Overflow flag

Bit [1]—(PSW.7) User defined flag

Bit [0]—P → (PSW.7) Parity flag, affected by hardware to indicate odd/even number of

―one‖ bits in the Accumulator (i.e., even parity)

The state of Bits RS1 and RS0 selects the working registers bank as presented in Table 25.

Table 25. RS1/RS0 Bank Selections by State

RS1/RS0

Bank selected location

Bank 0 (00H

–07H)

Bank 1 (08H

–0FH)

Bank 2 (10H

–17H)

Bank 3 (18H

–1FH)

4.8.4

Stack Pointer (SP)

Table 26 presents the stack pointer, which is a 1-byte register initialized to 07H after reset. This

08H. The stack pointer points to a location in internal RAM.

Table 26. Stack Pointer

SP.7

SP.6

SP.5

SP.4

SP.3

SP.2

SP.1

SP.0

4.8.5

Data Pointer (DPTR)

The data pointer (DPTR) is two bytes wide. Table 27 presents the highest, which is DPH.

Table 28 presents the lower part, DPL. It can be loaded as a 2-byte register (MOV

DPTR,#data16) or as two registers (MOV DPL,#data8 each). It is generally used to access

external code (MOVC A,@A+DPTR each) or data space (MOV A,@DPTR).

Table 27. Data Pointer (High) Register

DPH.7

DPH.6

DPH.5

DPH.4

DPH.3

DPH.2

DPH.1

DPH.0

Table 28. Data Pointer (Low) Register

DPL.7

DPL.6

DPL.5

DPL.4

DPL.3

DPL.2

DPL.1

DPL.0

TP8044AH-R0117 Scheda tecnica(PDF) 33 Page - InnovASIC, Inc

TP8044AH-R0117 Scheda tecnica(HTML) 33 Page - InnovASIC, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Scheda tecnica Scarica

Link URL