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ADRF6750ACPZ-R7 Scheda tecnica(PDF) 6 Page - Analog Devices |
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ADRF6750ACPZ-R7 Scheda tecnica(HTML) 6 Page - Analog Devices |
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6 / 40 page ![]() ADRF6750 Rev. A | Page 6 of 40 SPI Interface Timing Table 3. Parameter1 Symbol Limit Unit CLK Frequency fCLK 20 MHz max CLK Pulse Width High t1 15 ns min CLK Pulse Width Low t2 15 ns min Start Condition Hold Time t3 5 ns min Data Setup Time t4 10 ns min Data Hold Time t5 5 ns min Stop Condition Setup Time t6 5 ns min SDO Access Time t7 15 ns min CS to SDO High Impedance t8 25 ns max 1 See Figure 3. t1 t3 CS CLK SDI SDO t6 t8 t7 t2 t5 t4 Figure 3. SPI Port Timing Diagram |
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