ADRF6750ACPZ-R7 datasheet(15/40 Pages) AD

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ADRF6750

Rev. A | Page 15 of

0.1

100

10k

100k

10M

100M

–50 –25

100 125 150 175 200 225 250

TIME (µs)

CR23[3] = 1

CR23[3] = 0

LDET

ACQUISITION

TO 100Hz

START OF ACQUISITION

ON CR0 WRITE

Figure 35. PLL Frequency Settling Time at Worst-Case Low Frequency

with Lock Detect Shown

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

LO FREQUENCY (MHz)

Figure 36. Attenuator Gain vs. LO Frequency by Gain Code,

All Attenuator Code Steps

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

LO FREQUENCY (MHz)

Figure 37. Attenuator Relative Step Accuracy over all Attenuation Steps

vs. LO Frequency, Nominal Conditions

–0.8

–1.0

–0.6

–0.4 –0.2

ATTENUATOR RELATIVE STEP ACCURACY (dB)

0.2

0.4

0.6

0.8

1.0

NOMINAL

WORST CASE

Figure 38. Attenuator Relative Step Accuracy Distribution at Nominal

and Worst-Case Conditions

ATTENUATOR RELATIVE STEP ACCURACY ACROSS

FULL OUTPUT FREQUENCY RANGE (dB)

NOMINAL

WORST CASE

Figure 39. Attenuator Relative Step Accuracy Across Full Output

Frequency Range Distribution at Nominal and Worst-Case Conditions

–1.5

–1.3

–0.9

–1.1

–0.7

–0.5

–0.1

–0.3

0.1

0.5

0.3

LO FREQUENCY (MHz)

Figure 40. Attenuator Relative Step Accuracy over all Attenuation Steps

vs. LO Frequency for External VCO Mode, Nominal Conditions

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