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USB-TO-GPIO Scheda tecnica(PDF) 45 Page - Texas Instruments

Il numero della parte USB-TO-GPIO
Spiegazioni elettronici  USB Interface Adapter Evaluation Module
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USB-TO-GPIO Scheda tecnica(HTML) 45 Page - Texas Instruments

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B.15 Read Word Command and Response
B.16 Process Call Command and Response
Read Word Command and Response
USB PACKET
COMMAND
BYTE 0
USB PACKET USB PACKET
USB PACKET USB PACKET USB PACKET
USB PACKET
COMMENTS
DESCRIPTION
COMMAND
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTES 6–63
CODE
Read Word
0x06
A
B
C
USB PACKET
COMMAND
BYTE 0
USB PACKET USB PACKET
USB PACKET USB PACKET USB PACKET
USB PACKET
COMMENTS
DESCRIPTION
COMMAND
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTES 6–63
CODE
Low byte of
High byte of
Response from
Success: 0
0x86
word read
word read
Read Word
Fail: 1
from slave
from slave
The following describes the detailed bit banking of the Read Word command (with PEC on):
PMBUS/SMBUS start
→ write A (= slave address shifted left by 1 bit + write bit of 0) → slave ACK
→ write B (a command byte defined by PMBUS or SMBUS) → slave ACK → repeated start → write
C (= slave address shifted left by 1 bit + read bit of 1)
→ slave ACK → read in the low byte of a data
word from slave
→ master ACK → read in the high byte of the data word from slave → master ACK
→ read in PEC byte from slave → master NACK → PMBUS/SMBUS stop
USB PACKET
COMMAND
BYTE 0
USB PACKET USB PACKET
USB PACKET USB PACKET USB PACKET
USB PACKET
COMMENTS
DESCRIPTION
COMMAND
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTES 6–63
CODE
Process Call
0x07
A
B
C
D
E
USB PACKET
COMMAND
BYTE 0
USB PACKET USB PACKET
USB PACKET USB PACKET USB PACKET
USB PACKET
COMMENTS
DESCRIPTION
COMMAND
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTES 6–63
CODE
Low byte of
High byte of
Response from
Success: 0
0x87
word read
word read
Process Call
Fail: 1
from slave
from slave
The following describes the detailed bit banking of the Process Call command (with PEC on):
PMBUS/SMBUS start
→ write A (= slave address shifted left by 1 bit + write bit of 0) → slave ACK
→ write B (a command byte defined by PMBUS or SMBUS) → slave ACK → write C (low byte of a
data word)
→ slave ACK → write D (high byte of the data word) → slave ACK → repeated start →
write E (= slave address shifted left by 1 bit + read bit of 1)
→ slave ACK → read in the low byte of
a data word from slave
→ master ACK → read in the high byte of the data word from slave →
master ACK
→ read in PEC byte from slave → master NACK → PMBUS/SMBUS stop
SLLU093 – August 2006
PMBUS/SMBUS Communications
45
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