ADS1278IPAPR datasheet(27/51 Pages) TI1

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MODE[1:0]

Pins

ADS1274/78

Mode

NewMode

ValidDataReady

DRDY

SPI

Protocol

Frame-Sync

Protocol

NDR-SPI

DOUT

NewMode

ValidDataonDOUT

NDR-FS

Mode

ADS1274

ADS1278

www.ti.com

SBAS367F

– JUNE 2007 – REVISED FEBRUARY 2011

Figure 72. Mode Change Timing

Table 10. New Data After Mode Change

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tNDR-SPI

Time for new data to be ready (SPI)

129

Conversions (1/fDATA)

tNDR-FS

Time for new data to be ready (Frame-Sync)(1)

127

128

Conversions (1/fDATA)

(1)

If mode change is asynchronous to the FSYNC clock, tNDR-FS varies from 127 to 128 conversions. If the mode change is made

synchronous to FSYNC, tNDR-FS is stable.

SYNCHRONIZATION (SYNC)

See Figure 74 for the Frame-Sync format timing

requirement.

The ADS1274/78 can be synchronized by pulsing the

SYNC pin low and then returning the pin high. When

After

synchronization,

indication

valid

data

the pin goes low, the conversion process stops, and

depends on whether SPI or Frame-Sync format was

the internal counters used by the digital filter are

used.

reset.

When

the

SYNC

returns

high,

the

conversion process restarts. Synchronization allows

In the SPI format, DRDY goes high as soon as SYNC

the conversion to be aligned with an external event,

is taken low; see Figure 73. After SYNC is returned

such as the changing of an external multiplexer on

high, DRDY stays high while the digital filter is

the analog inputs, or by a reference timing pulse.

settling. Once valid data are ready for retrieval,

DRDY goes low.

Because the ADS1274/78 converters operate in

parallel from the same master clock and use the

In the Frame-Sync format, DOUT goes low as soon

same SYNC input control, they are always in

as SYNC is taken low; see Figure 74. After SYNC is

synchronization with each other. The aperture match

returned high, DOUT stays low while the digital filter

among internal channels is typically less than 500ps.

is settling. Once valid data are ready for retrieval,

However, the synchronization of multiple devices is

DOUT begins to output valid data. For proper

somewhat different. At device power-on, variations in

synchronization, FSYNC, SCLK, and CLK must be

internal reset thresholds from device to device may

established before taking SYNC high, and must then

result in uncertainty in conversion timing.

remain running. If the clock inputs (CLK, FSYNC or

SCLK)

are

subsequently

interrupted

reset,

The SYNC pin can be used to synchronize multiple

re-assert the SYNC pin.

devices to within the same CLK cycle. Figure 73

illustrates the timing requirement of SYNC and CLK

For consistent performance, re-assert SYNC after

in SPI format.

device power-on when data first appear.

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