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ADS1278IPAPR Scheda tecnica(PDF) 4 Page - Texas Instruments

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Il numero della parte ADS1278IPAPR
Spiegazioni elettronici  Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters
PDF  51 Pages
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1278IPAPR Scheda tecnica(HTML) 4 Page - Texas Instruments

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ADS1274
ADS1278
SBAS367F
– JUNE 2007 – REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Crosstalk
f = 1kHz,
–0.5dBFS(5)
–107
dB
High-Speed mode
101
106
dB
VREF = 2.5V
103
110
dB
High-Resolution mode
Signal-to-noise ratio (SNR)(6)
VREF = 3V
111
dB
(unweighted)
Low-Power mode
101
106
dB
Low-Speed mode
101
107
dB
Total harmonic distortion (THD)(7)
VIN = 1kHz, –0.5dBFS
–108
–96
dB
Spurious-free dynamic range
109
dB
Passband ripple
±0.005
dB
Passband
0.453 fDATA
Hz
–3dB Bandwidth
0.49 fDATA
Hz
High-Resolution mode
95
dB
Stop band attenuation
All other modes
100
High-Resolution mode
0.547 fDATA
127.453 fDATA
Hz
Stop band
All other modes
0.547 fDATA
63.453 fDATA
Hz
High-Resolution mode
39/fDATA
s
Group delay
All other modes
38/fDATA
s
High-Resolution mode
Complete settling
78/fDATA
s
Settling time (latency)
All other modes
Complete settling
76/fDATA
s
VOLTAGE REFERENCE INPUTS
Negative reference input (VREFN)
AGND
– 0.1
AGND + 0.1
V
0.1
≤ fCLK ≤ 27MHz
0.5
2.5
3.1
V
Reference input voltage (VREF)
(8)
27
< fCLK ≤ 32.768MHz
0.5
2.5
2.6
V
(VREF = VREFP – VREFN)
32.768MHz
< fCLK ≤ 37MHz
0.5
2.048
2.1
V
High-Speed mode
1.3
k
Ω
High-Resolution mode
1.3
k
Ω
ADS1274
Reference Input impedance
Low-Power mode
2.6
k
Ω
Low-Speed mode
13
k
Ω
High-Speed mode
0.65
k
Ω
High-Resolution mode
0.65
k
Ω
ADS1278
Reference Input impedance
Low-Power mode
1.3
k
Ω
Low-Speed mode
6.5
k
Ω
DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)
VIH
0.7 IOVDD
IOVDD
V
VIL
DGND
0.3 IOVDD
V
VOH
IOH = 4mA
0.8 IOVDD
IOVDD
V
VOL
IOL = 4mA
DGND
0.2 IOVDD
V
Input leakage
0
< VIN DIGITAL < IOVDD
±10
μA
High-Speed mode(8)
0.1
37
MHz
Master clock rate (fCLK)
Other modes
0.1
27
MHz
(5)
Worst-case channel crosstalk between one or more channels.
(6)
Minimum SNR is ensured by the limit of the DC noise specification.
(7)
THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
(8)
fCLK = 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for VREF restrictions in High-Speed mode.
4
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© 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1274 ADS1278



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