95

90

85

80

75

70

65

60

Differential Clock Amplitude

− V

0

0.5

1.0

1.5

2.0

2.5

3.0

f

SFDR

SNR

INTERNAL DLL

OUTPUT INFORMATION

ADS5520

Figure 49. AC Performance vs Clock Amplitude

In order to obtain the fastest sampling rates achievable with the ADS5520, the device uses an internal digital

delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance

at clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must be

shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical

Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL

OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The

limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz.

The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal

(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the

full-scale limits.

Two different output formats (straight offset binary or 2's complement) and two different output clock polarities

(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one

of four different voltages. Table 4 details the four modes. In addition, output enable control (OE, pin 41, active

high) is provided to put the outputs into a high-impedance state.

In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive

overdrive, the output code is 0xFFF in straight offset binary output format and 0x7FF in 2's complement output

format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x800

in 2's complement output format. These outputs to an overdrive signal are ensured through design and

characterization.

The output circuitry of the ADS5520, by design, minimizes the noise produced by the data switching transients,

and, in particular, its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance and

adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in

the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have

nearly the same load as D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply

voltage or temperature. Placing external resistors in series with the outputs is not recommended.

The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximum

sampling frequency. Table 6 and Table 7 show the setup, hold, input clock to output data delays, and rise and

fall times for different sampling frequencies with the DLL on and off, respectively.

Table 8 and Table 9 show the rise and fall times at additional sampling frequencies with DLL on and off,

respectively.

28

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