MP2007 – 3A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR

MP2007 Rev. 0.9

www.MonolithicPower.com

7

7/23/2009

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DETAILED OPERATING DESCRIPTION

VREF

VDDQ

VTT

VTT

Regulation

& Deadband

Control

Current

Limiter

Current

Limiter

Soft-Start

VTTSEN

VDRV

UVLO

DDQ

DDQ

UVLO

VTTREF

VDRV

5V

VEN

GND

REF

EN

DDQ

VTTSEN

VTTREF

VTT

Figure 1—Functional Block Diagram

Control Logic

The internal control logic is powered by VDRV.

The IC is enabled whenever both VDDQ UVLO

and VDRV UVLO are pulled low. VTTREF output

begins to track VREF/2. When the VTTEN pin is

high, the VTT regulator is activated.

VTTREF Output

The VTTREF output tracks VREF/2 with

±2%

accuracy. It has source current capability of up to

15 mA. VTTREF should be bypassed to analog

ground of the device by 1.0

μF ceramic capacitor

for stable operation.

The VTTREF is turned on as long as both VDDQ

and VDRV are higher the UVLO threshold.

VTTREF features a soft-start and tracks VREF/2.

Output Voltages Sensing

The VTT output voltage is sensed across the

VTTSEN and GND pins. The VTTSEN should be

connected to the VTT regulation point, which is

usually the VTT local bypass capacitor, via a

direct sense trace. The GND should be

connected via a direct sense trace to the ground

of the VTT local bypass capacitor for load.

VDDQ UVLO Protection

For

VDDQ

undervoltage

lockout

(UVLO)

protection, the MP2007 monitors VDDQ voltage.

When the VDDQ voltage is lower than UVLO

threshold voltage, the VTT regulator is shut off.

Current Protection of VTT Active Terminator

To provide protection for the internal FETs, over

current limit(OCL) of 3A is implemented.

The LDO has a constant overcurrent limit (OCL)

at 3.5 A. This trip point is reduced to 1.0 A if the

output voltage drops below 1/3 of the target

voltage.