AS3543 datasheet(79/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 81. RAM & WakeUp Register

Name

Base

Default

RAM & WakeUp

2-wire serial

00h

Offset: 22h

RAM & WakeUp Register

Sets and enables the RTC wake-up counter and programs the 128bit SRAM.

3 bytes need to be written in a sequence to set the counter. The MSB of the

byte enables the wake-up counter. Byte 4 …19 will program the static

128bit SRAM which is supplied by RVDD. This register keeps its content during

normal shut-down and is only reset at a RVDD-POR.

Bit

Byte Name

Default

Access

Bit Description

7:0

WAKE_UP_BYTE_0

write to 0x19 is

byte 0)

00h

R/W

0000 0001b: 1sec

0000 0010b: 2sec

0000 0100b: 4sec

0000 1000b: 8sec

0001 0000b: 16sec

0010 0000b: 32sec

0100 0000b: 64sec

1000 0000b: 128sec

7:0

WAKE_UP_BYTE_1

write to 0x19 is

byte 1)

00h

R/W

0000 0001b: 256sec

0000 0010b: 512sec

0000 0100b: 1 024sec

0000 1000b: 2 048sec

0001 0000b: 4 096sec

0010 0000b: 8 192sec

0100 0000b: 16 384sec

1000 0000b: 32 768sec

7:0

WAKE_UP_BYTE_2

write to 0x19 is

byte 2)

00h

n/a

000 0001b: 65 536sec

000 0010b: 131 072sec

000 0100b: 262 144sec

000 1000b: 524 288sec

001 0000b: 1 048 576sec

010 0000b: 2 097 152sec

100 0000b: 4 194 304sec

0xxx xxxxxb = wake-up disabled

1xxx xxxxxb = wake-up enabled

7:0

SRAM_128<0:15>

… 19

write to

0x22 programs the

128bit static SRAM)

00h

R/W

xxxx xxxxb = byte 0

xxxx xxxxb = byte 15

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