AS3543 datasheet(45/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s

10.1.3 Start-up Sequence

The AFE offers different power-up sequences. While VPRG1 and VPRG2 pins are defining the regulator voltages

VPRG3 is setting the sequence of powering on the regulators during the start-up. These pins detect 5 logical input

states which shall come from an external resistor divider network.

At first, LDO2 (AVDD27) and LDO1 (AVDD17) are powered up. This cannot be influenced with the selection of specific

sequences below. LDO2 is necessary for the internal supply of the AFE, LDO1 could be turned off later if no audio

functionality is needed.

After power-up sequence all voltage settings and power on/off conditions of the described regulators can be pro-

grammed via the serial interface

10.1.4 XRES delay with PWGD pin

With using an exteral capacitor on PWGD, the XRES signal can be delayed. This delay can be calculated with the

10uA pull-up current and a comparator threshold of ~1V. Using a 100nF capacitance will give a delay of 10ms.

Table 30. Start-Up Sequence

CVDD1

CVDD2

PVDD1

PVDD2

VPRG1 (core)

vdd

0.8V

150k PU

1. pull ups (PU) must be connected to AVDD27

1.5V

open

1.2V

150k PD

2. pull downs (PD) shall be connected to DVSS

vss

1.0V

VPRG2 (peri)

vdd

2.5V

3.3V

150k PU

2.8V

1.8V

3.3V

open

1.8V

3.3V

150k PD

vss

3.3V

VPRG3 (sequence)

vdd

off

150k PU

open

150k PD

vss

off

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