CS5181 datasheet(6/24 Pages) CIRRUS

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CS5181

DS250PP1

SWITCHING CHARACTERISTICS (T

A = -40 to 85 °C; VA+ = 5 V ±5%, VD+ = 3.3 V ±0.3 V;

AGND = DGND = 0 V; MODE = VD+)

Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform.

11. RESET, SYNC, and PWDN have Schmitt-trigger inputs.

12. Specifications applicable to complementary signals SCLK and SDO.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 2)

MCLK

0.512

25 to 40

MHz

Master Clock Duty Cycle

Rise Times

(Notes 2, 10, and 11)

Any Digital Input, Except MCLK

MCLK

Any Digital Output

trise

100

.2/MCLK

Fall Times

(Notes 2, 10, and 11)

Any Digital Input, Except MCLK

MCLK

Any Digital Output

tfall

100

.2/MCLK

Calibration/Sync

RESET rising to MCLK rising

-3

RESET rising recognized, to FSO falling

988205/MCLK

SYNC rising to MCLK rising

SYNC rising recognized to FSO falling

5161/MCLK

PWDN rising recognized to FSO falling

5168/MCLK

SYNC high time

1/MCLK

RESET low time

1/MCLK

Serial Port Timing

(Note 12)

SCLK frequency

MCLK/3

SCLK high time

-1/MCLK

SCLK low time

-2/MCLK

FSO falling to SCLK rising

-2/MCLK + 2E-9

SCLK falling to new data bit

-1.5

SCLK rising to FSO rising

-1/MCLK - 2E-9

FSO

SCLK

SDATA XX

MSB

MSB-1

LSB-1

LSB

Figure 1. Serial Port Timing (not to scale)

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