CS5181 datasheet(9/24 Pages) CIRRUS

9 / 24 page

CS5181

DS250PP1

is not necessary to make the converter operate

properly. If it is unused it should be tied to DGND.

Conversion data is output from the SDO and SDO

pins of the device. The data is output from the SDO

pin MSB first, in two’s complement format. The

converter furnishes a serial clock SCLK and its

complement SCLK to latch the data bits; and a data

frame signal, Frame Signal Output (FSO), which

frames the output conversion word. The SCLK

output frequency is MCLK/3.

Clock Generator

The CS5181 must be driven from a CMOS-com-

patible clock at its MCLK pin. The MCLK input is

powered from the VD+ supply and its signal input

should not exceed this supply.

The required

MCLK is 64 × OWR (Output Word Rate). To

achieve an Output Word Rate of 625 kHz, the

MCLK frequency must be 64 × 625 kHz, or

40 MHz. A second clock input pin, MCLK, is not

actually used inside the device but allows the user

to run a fully differential clock to the converter to

minimize radiated noise from the PC board layout.

The CS5181 can be operated with MCLK frequen-

cies from 512 kHz up to 40 MHz. The output word

rate

scales

with

the

MCLK

rate

with

OWR = MCLK/64.

Voltage Reference

The CS5181 can be configured to operate from ei-

ther its internal voltage reference, or from an exter-

nal voltage reference.

The on-chip voltage reference is nominally 2.375 V

and is referenced to the AGND pins. This 2.375 V

reference is output from the VREFOUT pin. It is

then filtered and returned to the VREFIN pin. The

VREFIN pin is connected to a buffer which has a

typical gain of 1.6. This scales the on-chip reference

of 2.375 V to 3.8 V. This value sets the peak-to-peak

input voltage into the AIN pins of the converter. Fig-

ure 3 illustrates the CS5181 connected to use the in-

ternal voltage reference. Note that a 1.0 µF and 0.1

µF capacitor are shown connected to the VREFCAP

pin to filter out noise. A larger capacitor can be used,

but may require a longer reset period when first pow-

ering up the part to allow for the reference to stabilize

before the part self-calibrates.

Alternatively, the CS5181 can be configured to use

an external voltage reference. Figure 4 illustrates

the CS5181 connected to use a 2.5 V external ref-

erence. In this case, the maximum peak-to-peak

signal input at the AIN pins is 4.0 V.

10 µF

0.1 µF

VREFIN

VREF+

VREF-

VREFOUT

VREFCAP

X1.6

Modulator

Reference

CS5181

10 µF

0.1 µF

1 µF

0.1 µF

Figure 3. CS5181 connection diagram for using the internal voltage reference.

CS5181 Scheda tecnica(PDF) 9 Page - Cirrus Logic

CS5181 Scheda tecnica(HTML) 9 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Scheda tecnica Scarica

Link URL