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DS80C400 Scheda tecnica(PDF) 13 Page - Dallas Semiconductor |
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DS80C400 Scheda tecnica(HTML) 13 Page - Dallas Semiconductor |
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13 / 97 page ![]() DS80C400 Network Microcontroller 13 of 97 ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1) (VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) 75MHz VARIABLE CLOCK PARAMETER SYMBOL MIN MAX MIN MAX UNITS External Crystal Frequency 4 40 Clock Mutliplier 2X Mode 16 37.5 Clock Multiplier 4X Mode 1 / tCLK 11 18.75 MHz External Oscillator Frequency DC 75 Clock Mutliplier 2X Mode 16 37.5 Clock Multiplier 4X Mode 1 / tCLK 11 18.75 MHz PSEN Pulse Width tPLPH 21.7 2tCLCL - 5 ns PSEN Low to Valid Instruction In tPLIV 9.7 2tCLCL - 17 ns Input Instruction Hold After PSEN tPXIX 0 0 ns Input Instruction Float After PSEN tPXIZ See MOVX Characteristics ns Port 7 Address to Valid Instruction In tAVIV1 21.0 3tCLCL - 19 ns Port 2, 4, 6 Address or Port 4 CE to Valid Instruction In tAVIV2 27.7 3tCLCL + tCLCH - 19 ns Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted. Note 3: tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in the the System Clock Time Periods table. Note 4: The precalculated 75MHz min/max timing specifications assume an exact 50% duty cycle. Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 ( CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7). Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing absolute signal timing with respect to the external clock. |
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