ZIOL2102 datasheet(69/91 Pages) ETC2

69 / 91 page

ZIOL2xxx – IC Family

IO-Link compliant HV Line Driver IC Family

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

69 of 90

Name

Description

Remarks

Usage

1) /

Connection

Application Circuit Restrictions

and/or Remarks

AUX _TX

TX: Data input

Digital IN

Required or

open/-

Pin tolerates 5V logic signals

AUX _RX

RX: Data output

Digital OUT Required or

open/-

AUX_O

AUX driver OUT

4) OUT

Required or

open/-

AUX _I

AUX driver IN

4) IN

Required or

open/-

DC_RDY

DC/DC ready signal

Digital OUT Required or

open/-

DC/DC switch OUT

HV OUT

Required or

open/-

DC/DC feed back

Analog IN

Required / either

interconnected

voltage divider or

to LR_OUT

In operation mode of the DC/DC

converter the voltage divider shall

provide 1.225V at the FB pin.

Interconnecting FB to LR_OUT

will disable the DC/DC converter.

LR_IN

Linear regulator Input

Voltage (HV

4))

Supply IN

Required/-

LR_OUT

Linear regulator Output

Voltage (LV

5))

Supply

OUT LV

Required/ Block

Cap to VSS

1) Names of low active digital I/O pins end with “_L”

2) Usage: If “Required” is specified, an electrical connection is necessary – refer to the application circuits

3) Connection: To be connected to this potential, if not used or no application/configuration related constraints are given

4) HV: High voltage – The primary supply voltage of the IC or the voltage swing of the cable signal, typically 24V (>8V, <36V)

5) LV: Low voltage – The supply voltage for the internal building blocks of the IC or control signals of the IC, typically 3.3V

5.2.

ESD-Protection

All pins have an ESD protection of >2000 V.

ESD protection referred to the Human Body Model (HBM) is tested with devices in QFN24 packages during

product qualification. The ESD test follows the Human Body Model with 1.5 kΩ/100 pF, based on MIL 883,

Method 3015.7.

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