HT47C20 datasheet(24/56 Pages) HOLTEK

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HT47C20

January 18, 2000

A/D converter

Two channels of RC type A/D converter are im-

plemented in the HT47C20. The A/D converter

contains two 16-bit programmable count-up

counter and the Timer A clock source may come

from the system clock, instruction clock or RTC

output. The timer B clock source may come

from the external RC oscillator. The TMRAL,

TMRAH, TMRBL, TMRBH is composed of the

A/D converter when ADC/TM bit (bit 1 of ADRC

The A/D converter timer B clock source may

come from channel 0 (IN0 external clock input

mode, RS0~CS0 oscillation, RT0~CS0 oscilla-

tion, CRT0~CS0 oscillation (CRT0 is a resis-

tor), or RS0~CRT0 oscillation (CRT0 is a

capacitor) or channel 1 (RS1~CS1 oscillation,

RT1~CS1 oscillation or IN1 external clock in-

put). The timer A clock source is from the sys-

tem clock, instruction clock or RTC prescaler

clock output decided by TMRC register.

There are six registers related to the A/D con-

verter, i.e., TMRAH, TMRAL, TMRC, TMRBH,

TMRBL and ADCR. The internal timer clock is

input to TMRAH and TMRAL, the A/D clock is

input to TMRBH and TMRBL. The OVB/OVA

bit (bit 0 of ADCR register) decides whether

timer A overflows or timer B overflows, then

the TF bit is set and timer interrupt occurs.

When the A/D converter mode timer A or timer

B overflows, the TON bit is reset and stop

counting. Writing TMRAH/TMRBH makes the

starting value be placed in the timer A/timer B

and reading TMRAH/TMRBH gets the con-

tents of the timer A/timer B. Writing

TMRAL/TMRBL only writes the data into a low

byte buffer, and writing TMRAH/TMRBH will

write the data and the contents of the low byte

buffer into the timer A/timer B (16-bit) simulta-

neously. The timer A/timer B is changed by writ-

ing TMRAH/TMRBH operations and writing

TMRAL/TMRBL will keep timer A/timer B un-

changed.

Reading TMRAH/TMRBH will also latch the

TMRAL/TMRBL into the low byte buffer to avoid

thefalsetimingproblem.ReadingTMRAL/TMRBL

returns the contents of the low byte buffer. In other

word, the low byte of timer A/timer B can not be

read directly. It must read the TMRAH/TMRBH

first to make the low byte contents of timer A/timer

Bbelatchedintothebuffer.

Label

(ADCR)

Bits

Function

OVB/OVA

In the RC type A/D converter mode, this bit is used to define the timer/event

counter interrupt which comes from timer A overflow or timer B overflow.

(0= timer A overflow; 1= timer B overflow)

In the timer/event counter mode, this bit is void.

ADC/TM

Defines 16 timer/event counters or RC type A/D converter is enabled.

(0= timer/event counter enable; 1= A/D converter is enabled)

2~3 Unused bits, read as ²0².

Defines the A/D converter operating mode (M3, M2, M1, M0)

0000= IN0 external clock input mode

0001= RS0~CS0 oscillation (reference resistor and reference capacitor)

0010= RT0~CS0 oscillation (resistor sensor and reference capacitor)

0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor)

0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor)

0101= RS1~CS1 oscillation (reference resistor and reference capacitor)

0110= RT1~CS1 oscillation (resistor sensor and reference capacitor)

0111= IN1 external clock input mode

1XXX= Undefined mode

ADCR register

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