HT48C50- datasheet(19/45 Pages) HOLTEK

19 / 45 page

HT48C50-1

June 14, 2000

Preliminary

or to generate an accurate time base and PFD

signals.

Using the internal clock sources, there are 2

reference time-bases for timer/event counter 1.

The internal clock source can be selected as

coming from fSYS/4 (can always be optioned) or

fRTC (enable only the system oscillator in the

Int. RC+RTC mode) by mask option. The exter-

nal clock input allows the user to count external

events, measure time intervals or pulse widths

or to generate an accurate time base.

There are 2 registers related to the timer/event

counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two

physical registers are mapped to TMR0 location;

writing TMR0 makes the starting value be placed

in the timer/event counter 0 preload register and

readingTMR0getsthecontentsofthetimer/event

counter 0. The TMR0C is a timer/event counter

controlregister,whichdefinessomeoptions.

There are 3 registers related to timer/event

counter 1; TMR1H (0FH), TMR1L (10H),

TMR1C (11H). Writing TMR1L will only put

the written data to an internal lower-order byte

buffer (8 bits) and writing TMR1H will transfer

the specified data and the contents of the

lower-order byte buffer to TMR1H and TMR1L

preload registers, respectively. The timer/event

counter 1 preload register is changed by each

writing TMR1H operations. Reading TMR1H

will latch the contents of TMR1H and TMR1L

counters to the destination and the lower-order

byte buffer, respectively. Reading the TMR1L

will read the contents of the lower-order byte

buffer. The TMR1C is the timer/event counter 1

control register, which defines the operating

mode, counting enable or disable and active

edge.

The TM0, TM1 bits define the operating mode.

The event count mode is used to count external

events, which means the clock source comes

from an external (TMR0/TMR1) pin. The timer

mode functions as a normal timer with the

clock source coming from the fINT clock/instruc-

tion clock or RTC clock (Timer0/Timer1). The

pulse width measurement mode can be used to

count the high or low level duration of the external

signal (TMR0/TMR1). The counting is based on

the fINT clock/instruction clock or RTC clock

(Timer0/Timer1).

In the event count or timer mode, once the

timer/event counter 0/1 starts counting, it will

count from the current contents in the

timer/event counter 0/1 to FFH or FFFFH. Once

overflow occurs, the counter is reloaded from the

timer/event counter 0/1 preload register and gen-

erates the interrupt request flag (T0F/T1F; bit

5/6 of INTC) at the same time.

In the pulse width measurement mode with

the TON and TE bits equal to one, once the

TMR0/TMR1 has received a transient from low

to high (or high to low if the TE bits is "0") it will

start counting until the TMR0/TMR1 returns to

the original level and resets the TON. The mea-

sured result will remain in the timer/event

counter 0/1 even if the activated transient oc-

curs again. In other words, only one cycle mea-

surement can be done. Until setting the TON,

the cycle measurement will function again as

long as it receives further transient pulse. Note

that, in this operating mode, the timer/event

counter 0/1 starts counting not according to the

logic level but according to the transient edges.

In the case of counter overflows, the counter 0/1

is reloaded from the timer/event counter 0/1

preload register and issues the interrupt re-

quest just like the other two modes. To enable

the counting operation, the timer ON bit (TON;

bit 4 of TMR0C/TMR1C) should be set to 1. In

the pulse width measurement mode, the TON

will be cleared automatically after the mea-

surement cycle is completed. But in the other

two modes the TON can only be reset by in-

structions. The overflow of the timer/event

counter 0/1 is one of the wake-up sources. No

matter what the operation mode is, writing a 0

to ET0I/ET1I can disable the corresponding in-

terrupt services.

In the case of timer/event counter 0/1 OFF con-

dition, writing data to the timer/event counter

0/1 preload register will also reload that data to

the timer/event counter 0/1. But if the

timer/event counter 0/1 is turned on, data writ-

ten to it will only be kept in the timer/event

counter 0/1 preload register. The timer/event

counter 0/1 will still operate until overflow oc-

curs (a timer/event counter 0/1 reloading will oc-

HT48C50- Scheda tecnica(PDF) 19 Page - Holtek Semiconductor Inc

HT48C50- Scheda tecnica(HTML) 19 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Scheda tecnica Scarica

Link URL