HT49C10 datasheet(13/47 Pages) HOLTEK

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HT49C10

September 28, 1999

Bit No.

Label

Function

INTC0

(0BH)

EMI

Control the master (global) interrupt

(1= enabled; 0= disabled)

EEI0

Control the external interrupt 0

(1= enabled; 0= disabled)

EEI1

Control the external interrupt 1

(1= enabled; 0= disabled)

ETI

Control the timer/event counter interrupt

(1= enabled; 0= disabled)

EIF0

External interrupt 0 request flag

(1= active; 0= inactive)

EIF1

External interrupt 1 request flag

(1= active; 0= inactive)

6TF

Internal timer/event counter request flag

(1= active; 0= inactive)

Unused bit, read as ²0²

INTC1

(1EH)

ETBI

Control the time base interrupt

(1= enabled; 0= disabled)

ERTI

Control the real time clock interrupt

(1= enabled; 0= disabled)

2, 3

Unused bit, read as ²0²

TBF

Time base request flag

(1= active; 0= inactive)

RTF

Real time clock request flag

(1= active; 0= inactive)

6, 7

Unused bit, read as ²0²

INTC register

interrupt request flag (EIF0; bit 4 of INTC0,

EIF1; bit 5 of INTC0) is set as well. After the in-

terrupt is enabled, and the stack is not full, and

the external interrupt is active, a subroutine

call to location 04H or 08H occurs. The inter-

rupt request flag (EIF0 or EIF1) and EMI bits

are all cleared to disable other interrupts.

The internal timer/event counter interrupt is

initialized by setting the timer/event counter

interrupt request flag (TF; bit 6 of INTC0), that

is caused by a timer overflow. After the inter-

rupt is enabled, and the stack is not full, and

the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag

(TF) is reset, and the EMI bit is cleared to dis-

able further interrupts.

The time base interrupt is initialized by setting

the time base interrupt request flag (TBF; bit 4

of INTC1), that is caused by a regular time base

signal. After the interrupt is enabled, and the

stack is not full, and the TBF bit is set, a sub-

routine call to location 10H occurs. The related

interrupt request flag (TBF) is reset and the

EMI bit is cleared to disable further interrupts.

The real time clock interrupt is initialized by

setting the real time clock interrupt request

flag (RTF; bit 5 of INTC1), that is caused by a

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