HT49C10 datasheet(21/47 Pages) HOLTEK

21 / 47 page

HT49C10

September 28, 1999

Label (TMRC)

Bits

Function

0~2

Unused bits, read as ²0²

Defines the TMR active edge of the timer/event counter

(0=active on low to high; 1=active on high to low)

TON

Enable/disable timer counting

(0=disabled; 1=enabled)

TN2

Two to one multiplexer control inputs to select the timer/event counter

clock source (0=RTC output; 1=system clock or system clock/4)

TN0, TN1

7, 6

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse Width measurement mode (external clock)

00=Unused

TMRC register

the TON can only be reset by instructions. The

overflow of the timer/event counter is one of the

wake-up sources and can also be applied to a

PFD (Programmable Frequency Divider) out-

put at PA3 by mask option. No matter what the

operation mode is, writinga0toETI disables the

interrupt service. When the PFD function is se-

lected, executing ²CLR [PA].3² instruction to en-

able PFD output and executing ²SET [PA].3²

instruction to disable the PFD output.

In the case of timer/event counter OFF

condition, writing data to the timer/event counter

preload register also reloads that data to the

timer/event counter. But if the timer/event coun-

ter is turned on, data written to the

timer/event counter is kept only in the

timer/event counter preload register. The

timer/event counter still goes on operating un-

til an overflow occurs.

When the timer/event counter (reading TMR)

is read, the clock is blocked to avoid errors. As

this may results in a counting error, this

should be taken into account by the program-

mer.

It is strongly recommended to load first a spe-

cific value into the TMR register, then turn on

the timer/event counter for proper operation.

Because the initial value of TMR is unknown.

Input/output ports

There is an 8-bit bidirectional input/output port

and a 6-bit input port in the HT49C10, labeled

PA and PB, which are mapped to [12H] and

[14H] of the RAM, respectively. PA0~PA3 can

be configured as CMOS (output) or NMOS (in-

put/output) and with or without pull-high resis-

tor by mask option, PA4~PA7 always pull-high

and NMOS (input/output). PB can only be used

for input operation, and each bit on the port

with pull-high resistor. Both are for the input

operation, these ports are non-latched, that is,

the inputs should be ready at the T2 rising edge

of the instruction ²MOV A, [m]² (m=12H or

14H). For PA output operation, all data are

latched and remain unchanged until the output

latch is rewritten.

When the structures of PA are open drain

NMOS type, it should be noted that, before

reading data from the pads, a ²1² should be

written to the related bits to disable the NMOS

device. That is executing first the instruction

²SET [m].i² (i=0~7 for PA) to disable any related

NMOS device, and then ²MOV A, [m]² to get

stable data.

HT49C10 Scheda tecnica(PDF) 21 Page - Holtek Semiconductor Inc

HT49C10 Scheda tecnica(HTML) 21 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Scheda tecnica Scarica

Link URL