HT49C50 datasheet(25/52 Pages) HOLTEK

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HT49C50

August 18, 1999

D a t a bus

Wr i t e

C h i p R es et

R ead I / O

S y s t em W ak e- up ( P A onl y )

W eak

Pu l l - u p

PA0 ~ PA7

PB0 ~ PB7

PC 0 ~ PC 3

M a sk o p t i o n

( P A 0 ~ P A 3 , P C )

M a sk o p t i o n

VD D

Ma s k

opt i o n

(P A 0 ~

P A3 , PC )

VD D

Input/output ports

There are a 12-bit bidirectional input/output

port, an 8-bit input port in the HT49C50, labeled

PA, PB and PC which are mapped to [12H],

[14H] and [16H] of the RAM, respectively.

PA0~PA3 can be configured as CMOS (output)

or NMOS (input/output) with or without

pull-high resistor by mask option. PA4~PA7 are

always pull-high and NMOS (input/output). If you

choose NMOS (input), each bit on the port

(PA0~PA7) can be configured as a wake-up input.

PB can only be used for input operation, and each

bit on the port can be configured with pull-high re-

sistor. PC can be configured as CMOS output or

NMOS input/output with or without pull-high re-

sistor by mask option. All the port for the input op-

eration (PA, PB and PC), these ports are

non-latched, that is, the inputs should be ready at

the T2 rising edge of the instruction ²MOV A, [m]²

(m=12H or 14H). For PA, PC output operation, all

data are latched and remain unchanged until the

outputlatch is rewritten.

When the PA and PC structures are open drain

NMOS type, it should be noted that, before

reading data from the pads, a ²1² should be

written to the related bits to disable the NMOS

device. That is executing first the instruction

²SET [m].i² (i=0~7 for PA) to disable related

NMOS device, and then ²MOV A, [m]² to get

stable data.

After chip reset, these input lines remain at the

high level or are left floating (by mask option).

Each bit of these output latches can be set or

cleared by the ²SET [m].i² and ²CLR [m].i²

(m=12H or 16H) instructions.

Some instructions first input data and then fol-

low the output operations. For example, ²SET

[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read

the entire port states into the CPU, execute the

defined operations (bit-operation), and then

write the results back to the latches or to the ac-

cumulator.

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