HT49R50 datasheet(13/59 Pages) HOLTEK

13 / 59 page

HT49R50

October 22, 1999

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic

operations and provides the following func-

tions:

· Arithmetic operations (ADD, ADC, SUB,

SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data op-

eration but also changes the status register.

Status register - STATUS

The status register (0AH) is of 8 bits wide and

contains, a carry flag (C), an auxiliary carry flag

(AC), a zero flag (Z), an overflow flag (OV), a

power down flag (PD), and a watchdog time-out

flag (TO). It also records the status information

and controls the operation sequence.

Except the TO and PD flags, bits in the status

to other registers. Data written into the status

ations related to the status register, however,

may yield different results from those intended.

The TO and PD flags can only be changed by a

watchdog timer overflow, chip power-up, or

clearing the watchdog timer and executing the

"HALT" instruction. The Z, OV, AC, and C flags

reflect the status of the latest operations.

On entering the interrupt sequence or execut-

ing the subroutine call, the status register will

not be automatically pushed onto the stack. If

the contents of the status is important, and if

the subroutine is likely to corrupt the status

tions and save it properly.

Interrupts

The HT49R50 provides two external inter-

rupts, two internal timer/event counter inter-

rupts, an internal time base interrupt, and an

internal real time clock interrupt. The inter-

rupt control register 0 (INTC0;0BH) and inter-

rupt control register 1 (INTC1;1EH) both

contain the interrupt control bits that are used

to set the enable/disable status and interrupt

request flags.

Labels

Bits

Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

borrow from the high nibble into the low nibble in subtraction; otherwise AC is

cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by either a system power-up or executing the "CLR WDT" instruc-

tion. PD is set by executing the "HALT" instruction.

TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" in-

struction. TO is set by a WDT time-out.

Undefined, read as "0"

Status register

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