HT49R50 datasheet(20/59 Pages) HOLTEK

Il numero della parte	HT49R50

Spiegazioni elettronici	8-Bit Microcontroller

PDF	59 Pages

Scroll/Zoom	100%

Produttore elettronici	HOLTEK [Holtek Semiconductor Inc]

Homepage	http://www.holtek.com

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20 / 59 page

HT49R50

October 22, 1999

To guarantee that the system oscillator is started

and stabilized, the SST (System Start-up Timer)

provides an extra-delay of 1024 system clock

pulses when the system awakes from the HALT

state or during power up. Awaking from the

HALT state or system power-up, the SST delay is

added.

An extra SST delay is added during the

power-up period, and any wake-up from the

HALT may enable only the SST delay.

The functional unit chip reset status is shown

below.

000H

Interrupt

Disabled

Prescaler, Divider

Cleared

WDT, RTC, Time

Base

Cleared. After master

reset, WDT starts

counting

Timer/event

counter

Off

Input/output ports

Input mode

Points to the top of the

stack

RE S

VD D

S S T T i m e - out

Ch i p Re s e t

t SS T

Reset timing chart

WD T

HAL T

WD T

T i m e - out

Re s e t

Ex t e r n a l

RE S

Co l d

Re s e t

P o w e r - on D e t e c t i o n

XS T

10- bi t R i ppl e

C ount e r

OS C 1

W a r m R es et

Reset configuration

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