74HC_HCT32

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 5 — 4 September 2012

3 of 17

NXP Semiconductors

74HC32; 74HCT32

Quad 2-input OR gate

5.

Pinning information

5.1 Pinning

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 4.

Pin configuration DIP14, SO14 and (T)SSOP14

Fig 5.

Pin configuration DHVQFN14

32

1A

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

001aad101

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aad102

32

Transparent top view

2Y

3A

2B

3B

2A

4Y

1Y

4A

4B

1B

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

1A to 4A

1, 4, 9, 12

data input

1B to 4B

2, 5, 10,13

data input

1Y to 4Y

3, 6, 8, 11

data output

GND

7

ground (0 V)

14

supply voltage

Table 3.

Function table[1]

Input

Output

nA

nB

nY

LLL

LH

H

HL

H

HHH