GMS81C50 datasheet(70/99 Pages) HYNIX

Il numero della parte	GMS81C50

Spiegazioni elettronici	8-BIT SINGLE CHIP MICROCONTROLLERS

PDF	99 Pages

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Produttore elettronici	HYNIX [Hynix Semiconductor]

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70 / 99 page

HYUNDAI

GMS81C50 Series

13.2 WDT Interrupt Interval

WDT Interrupt (IFWDT) interval is determined by the in-

terrupt IFBIT interval of Basic Interval Timer and the val-

ue of WDT Register.

-Interval of IFWDT = (IFBIT interval) * (WDTR value)

-Interval of IFWDT : 512 us * 1 = 512 us (MIN>)

-65,536us * 63 = 4,128,768 us (MAX>)

As IFBIT (Basic Interval Timer Interrupt Request) is used

for input clock of WDT, Input clock cycle is possible from

512 us to 65,536 us by BTS. (at fex = 4MHz)

*At Hardware reset time ,WDT starts automatically.

Therefore, the user must select the CKCTLR, WDTR be-

fore WDT overflow.

-Reset WDTR value = 0F h,15

-interval of WDT = 65,536 * 15 = 983040 us

(about 1second )

Determine Interval of IFWDT

Interval of IFWDT = Value of WDTR

> Interval of IFBIT

WDTCL

WDTR5

WDTR4

WDTR3

WDTR2

WDTR1

WDTR0

W <00C8 h>

WDTR

Watch DOG Timer Register

WDTCL

Watch Dog Timer Operation

free-run

Automatically cleared, after one machine cycle

GMS81C50 Scheda tecnica(PDF) 70 Page - Hynix Semiconductor