GMS97C2051 datasheet(27/39 Pages) HYNIX

27 / 39 page

8-Bit CMOS Microcontorller

GMS97C1051/L1051

HYUNDAI MicroElectronics

Figure 3. Time/Counter 0 Input Clock Logic

Interrupt

System

The GMS97C1051/L1051 provides 3 interrupt

sources ( two external interrupts and timer inter-

rupt ) with two priority levels.

Figure 4 gives a

general overview of the interrupt sources and illus-

trates the request and control flags.

A low-priority interrupt can itself be interrupted by

a high-priority interrupt, but not by another low

priority interrupt.

A high-priority interrupt cannot

be interrupted by any other interrupt source.

If two requests of different priority levels are re-

ceived simultaneously,

the request of higher

priority is serviced.

If requests of the same prior-

ity level are received simultaneously, an internal

polling sequence determines which request is serv-

iced.

Thus within each priority level there is a

second priority structure determined by the polling

sequence like Table 6.

Figure 4. Interrupt Request Sources

IT0

TCON.0

TCON.1

IE0

EX0

IE.0

PX0

IP.0

P3.2/

INT0

IE.7

IT1

TCON.2

TCON.3

IE1

EX1

IE.2

PX1

IP.2

P3.3/

INT1

TF0

TCON.5

Timer 0 Overflow

ET0

IE.1

PT0

IP.1

High Priority

Low Priority

fosc

P3.4/T0

max fosc/24

TR 0

TCON

Gate

TMOD

fosc/12

Timer 0

Input Clock

Control

C/T

TMOD

P3.2/INT0

P3.3/INT1

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