82375EB datasheet(48/131 Pages) INTEL

48 / 131 page

82375EBSB

After data is written into BIOS Timer Register (BE1

andor BE0

must be asserted) the BIOS timer starts

decrementing until it reaches zero It ‘‘freezes’’ at zero until the new count value is written

Bit

Description

3116

Reserved

150

BIOS Timer Count Value

The initial count value is written to bits 150 to start the timer The value

read is the current value of the BIOS Timer

40 ADDRESS DECODING

Conceptually the PCEB contains two programmable address decoders one to decode PCI Bus cycles that

need to be forwarded to the EISA Bus or serviced internally and the other to decode EISA Bus cycles that

need to be forwarded to the PCI Bus Two decoders permit the PCI and EISA Buses to operate concurrently

(Figure 2) The PCEB can be programmed to respond to certain PCI memory or IO region accesses as well as

configuration space accesses to the PCEB’s internal configuration registers PCEB address decoding is dis-

cussed in Section 41

The EISA address decoder decodes EISA Bus cycles generated by the bus master (DMA controller ISA

compatible master or EISA compatible master) that need to be forwarded to the PCI Bus The EISA decode

logic can be programmed to respond to certain memory or IO region accesses

82375EB Scheda tecnica(PDF) 48 Page - Intel Corporation