UPD17015 datasheet(71/120 Pages) NEC

71 / 120 page

µPD17015

13.4

TIMING CONTROL BLOCKS FOR OUTPUTTING COMMON SIGNAL AND SEGMENT SIGNAL

Fig. 13-5 shows the configuration of the timing control blocks for outputting the common signal and segment signal.

The common signal output timing control block controls the timing of the common signal output on pins COM0 to

COM3.

The segment signal output timing control block controls the timing of the segment signal output on pins LCD0 to

LCD8.

The common signal and segment signal are output when the LCDEN flag of the LCD enable register is set to 1.

Setting the LCDEN flag to 0 turns off the entire LCD display. (See Fig. 13-6.)

When the LCD display is turned off, the signals output from pins COM0 to COM3 and pins LCD0 to LCD8 are held

low.

Fig. 13-5 Configuration of Timing Control Blocks for Outputting Common Signal and Segment Signal

LCD

LCDD0

LCDD8

COM

Segment

signal

Common

signal

Segment signal

output timing

control block

Basic clock for

timing control

LCDEN flag

Common signal

output timing

control block

Fig. 13-6 Configuration and Functions of LCD Enable Register

6AH

R/W

Read/write

Address

Name

Hold

Power-on

Clock-stop

Flag symbol

LCD enable register

Turns the entire LCD display on or off.

Turns the display off. (The output from all the segment and common pins is held low.)

Turns the display on.

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